With the rapid spread of intelligent devices such as computers, semiconductor devices are rapidly being developed. Currently, semiconductor devices are required to have high storage-capability as well as high operating speeds. To meet these requirements, technologies for manufacturing semiconductor devices are being developed to improve the degree of integration, the level of reliability, and the response times of semiconductor devices.
Generally, semiconductor memory devices are divided into volatile and nonvolatile memory devices. Examples of the nonvolatile memory devices include flash memory devices, McRAM devices, etc. In particular, the McRAM device includes a first gate electrode functioning as a flash memory and a second gate electrode functioning as a normal gate electrode in a single cell. Recently, attention has been drawn to the McRAM devices because the McRAM devices possess advantages such as low power dissipation, low manufacturing cost, and rapid information processing speed.
FIGS. 1a through 1c illustrate, in cross-sectional views, the results of process steps for fabricating a McRAM device according to a conventional method.
Referring to FIG. 1a, a substrate 1 including an active region 2 and a non-active region 3 is provided. A first gate electrode 10 is formed on the active region 2 in the substrate 1. For example, the first gate electrode 10 may function as a flash memory. The first gate electrode 10 comprises a dielectric layer pattern 5a, a first conducting layer pattern 7a, and an insulating layer pattern 9a. Spacers 11 are then formed on sidewalls of the first gate electrode 10.
Referring to FIG. 1b, an oxide layer 13 is formed on the substrate 1 except the region of the first gate electrode 10 and the spacers 11. Then, a second conducting layer 15 is deposited over the oxide layer 13, the first gate electrode 10, and the spacers 11. A mask layer 17 is formed on the second conducting layer 15.
Referring to FIG. 1c, an etching process is performed using the mask layer 17 as an etching mask. Some parts of the second conducting layer 15 and the oxide layer 13 are removed to form a second conducting layer pattern 15a and a gate oxide 13a. Then, the mask layer 17 is removed. As a result, a second gate electrode 19 comprising the gate oxide 13a and the second conducting layer pattern 15a is formed on the active region 2 of the substrate 1. Here, the second gate electrode 19 functions as a normal gate electrode.
However, during the etching process to form the second gate electrode 19, a portion of the second conducting layer 15 remains on one sidewall of the spacer 11. Such residual conducting layer 20 may cause deterioration of device characteristics and, therefore, has to be removed. However, when the residual conducting layer 20 is removed, the second conducting layer pattern 15a of the second gate electrode 19 may be damaged.
To obviate deterioration of device characteristics due to residual materials in a semiconductor device, U.S. Pat. No. 6,455,440 to Jeng discloses a method for preventing polysilicon stringers in a memory device. The method for preventing conductive stringers in a memory device according to the above-mentioned U.S. patent comprises forming a conductive structure with a vertical profile on a substrate, wherein said conductive structure has at least two level oxidation rates, lower portion of said conductive structure higher said oxidation rates; performing an oxidation process to a portion of said conductive structure, such that said vertical profile of said conductive structure is changed to an increasing width profile from lower to higher portion of said conductive structure, wherein said increasing width profile of said conductive structure helps for etching process control; and etching said conductive structure with said increasing width profile to form a plurality of electrically isolated regions without any conductive stringers.
As another example, U.S. Pat. No. 6,001,688 to Rizzuto discloses a method of eliminating poly stringers in a memory device. A method of making a flash memory device without poly stringers according to the above-mentioned U.S. patent comprises forming a stacked gate region on a substrate, forming one or more word lines in the stacked gate region, performing a self-aligned etch in regions adjacent to the one or more word lines, and performing an isotropic etch to remove any poly stringers in the regions adjacent the one or more word lines. Particularly, the method includes a poly stringer clean-up etch that removes the poly stringers after a self-aligned etch (SAE) step that is used to define the separate word lines. The clean-up etch is isotropic and laterally etches the poly stringers that were previously shielded by the angled ONO fence during the SAE, thereby preventing short circuit conditions between word lines and improving the manufacturability of the process.